In a complementary metal-oxide semiconductor (CMOS) image sensor, when miniaturization of pixels progresses, the opening area of a photodiode is reduced, and sensitivity is lowered. Further, the size of a pixel transistor is reduced, and random noise is worsened. As a result, signal/noise (S/N) ratio is lowered and image quality is degraded.
Therefore, it has been proposed to improve the S/N ratio by reducing the parasitic capacitance of a floating diffusion (FD) and improving the charge-voltage conversion efficiency.
The parasitic capacitance of the FD includes diffusion capacitance of the FD, capacitance of the gate electrode of an amplifying transistor connected to the FD through an FD wiring, capacitance of the FD wiring, and any other capacitance. The diffusion capacitance of the FD can be reduced by lowering the concentration of the N-type impurity of the FD. However, in this case, there is concern about a contact failure.
The capacitance of the gate electrode of the amplifying transistor can be reduced by reducing the size of the amplifying transistor. However, when the size of the amplifying transistor is reduced, random noise is worsened.
Further, the capacitance of the FD wiring can be reduced to some extent by devising a wiring layout. However, because the FD needs to be connected to the amplifying transistor, the wiring layout is limited based on a sharing system of pixels. Therefore, reducing the capacitance of the FD wiring by devising the wiring layout is difficult.
Therefore, there has been proposed a method of reducing the capacitance of the FD wiring by changing the entire periphery of the wiring layer to a low dielectric constant film (for example, refer to PTL 1).